This application claims the benefit of Application No. 99-34962, filed in Korea on Aug. 23, 1999, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a method of forming a polysilicon layer, and more particularly, to a method of forming a polysilicon layer for dual gates.
2. Discussion of the Related Art
A complementary MOSFET (CMOS) consisting of NMOS and PMOS is widely used in the integrated circuit field. As the size of devices is reduced, a p+ polysilicon gate is used for a PMOS device. Degradation of performance characteristics of devices using the p+ polysilicon gate, such as threshold voltage fluctuation and ruined reliance of gate insulating layers, has been observed. This device degradation is a result of penetration of boron into thin gate insulating layers or diffusion of boron into a channel region in a silicon substrate.
Referring to FIG. 1A, a gate oxide layer 2, 80 xc3x85-thick, is formed on an n-type silicon substrate 1. Referring to FIG. 1B, a first polysilicon layer 3, 1000 xc3x85-thick, is deposited on the gate oxide layer 2 by a low-pressure CVD (LPCVD) at 625xc2x0 C. Referring to FIG. 1C, a silicon nitride layer 4 is generated by nitridizing the first polysilicon layer 3 in NH3 at 900xc2x0 C. and a pressure of 120 mTorr. Next, the silicon nitride layer 4 is removed by dilute HF (not shown). Nitrogen atoms are distributed on a surface of the first polysilicon layer 3. Referring to FIG. 1D, a second polysilicon layer 5, 1000 xc3x85-thick, is deposited by LPCVD at 625xc2x0 C. Ion implantation of BF2+ on the second polysilicon layer 5 is performed with an implant dosage of 5xc3x971015 ions/cm2 and an implantation energy of 50 keV. A polysilicon oxide layer 6 is formed on an upper part of the second polysilicon layer 5 by a first annealing in O2 ambience at 800xc2x0 C. for 30 minutes followed by a second annealing in N2 ambience at 900xc2x0 C.
A nitrogen barrier in the first polysilicon layer 3 prevents fluorine ions from spreading out and also reduces an amount of fluorine ions in the gate oxide layer 6, thereby decreasing the penetration of boron due to fluorine ions. In a p+ polysilicon gate structure of at least two layers of polysilicon, an interface layer 31 between the first polysilicon layer 3 and the second polysilicon layer 5 or between the second polysilicon layer 5 and a third polysilicon layer (not shown) is nitridized by high temperature gas nitridization using NH3 or N2O, thereby generating and accumulating numerous nitrogen atoms at the interface layer 31 as well as at other interface layers between the gate oxide layer 2 and the first polysilicon layer 3. The nitrogen atoms are prevented from spreading out by the fluorine ions.
A conventional method of forming a polysilicon layer uses an active gas, such as NH3 to form an interface layer and requires a subsidiary gas supply. When an n+ gate of NMOS in dual gates is formed, diffusion of arsenic (As) as a dopant in the interface layer is delayed, thereby decreasing doping efficiency. Thus, a previous ion-implantation is required to overcome this decreased doping efficiency. Another dopant, such as phosphorous (P), which has relatively faster diffusion and activation rates than those of As, should be implanted inside the n+ gate to the proper depth. Moreover, dopants accumulate in the interface layer 31 due to diffusion delay to reduce the activation rate, thereby increasing a shear resistance of polysilicon.
Accordingly, the present invention is directed to a method of forming a polysilicon layer that substantially obviates one or more of the problems due to limitations and disadvantages of the related art. An object of the present invention is to provide a method of forming a polysilicon layer which prevents boron penetration in a PMOS.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method of forming a polysilicon layer includes the steps of: loading a semiconductor substrate in a CVD reactor wherein a gate insulating layer is formed on the substrate; decompressing the reactor; depositing a first polysilicon layer on the substrate by flowing an SiH4 gas into the reactor; forming a plurality of Sixe2x80x94N bonds on the first polysilicon layer by maintaining atmospheric pressure of the reactor by filling the reactor with a nitrogen gas; decompressing the reactor; and depositing a second polysilicon layer on the first polysilicon layer by flowing SiH4 gas into the reactor.
In another aspect of the claimed invention, a method of forming a polysilicon layer includes the steps of: loading a silicon wafer in a CVD vertical reactor, wherein a gate oxide layer is formed on the wafer and wherein the reactor maintains atmospheric pressure at 625xc2x0 C. and is purged by nitrogen; decompressing the reactor to 50.5 Pa; depositing a first polysilicon layer on the wafer by flowing an SiH4 gas into the reactor; forming a plurality of SiN bonds on the first polysilicon layer by maintaining atmospheric pressure of the reactor by filling the reactor with a nitrogen gas; decompressing the reactor to 50.5 Pa; and depositing a second polysilicon layer on the first polysilicon layer by flowing SiH4 gas into the reactor, wherein the second polysilicon layer is formed to be thicker than the first polysilicon layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.